1. Field of the Invention
The present invention relates to a power supply circuit for semiconductor memory, end, more particularly, to a power supply circuit for a semiconductor memory for the erasing and writing of electrically erasable programmable read-only memory (EEPROM).
2. Description of the Prior Art
The EEPROM is being used in a wide variety of applications because information stored therein can be changed from an external panel or through a remote operation while it is installed in a system.
The EEPROM stores information by charges contained in its cells. A high-field tunneling effect is utilized for the movement of charges in erasing/writing. Writing information to a cell is performed by applying to each node in the cell a voltage corresponding to the content of information, and moving the charges with the high field applied to the insulating film (tunneling implantation). Erasure of information is performed in such ways as by reversing the direction of the electrical field to discharge the accumulated charges. The reading of information is performed by utilizing the change in the threshold of the cell transistor because of the charges accumulated in correspondence to information.
Therefore the EEPROM requires a high voltage necessary for erasing/writing of the cell in addition to voltage for regular memory operation. Generally, it has a voltage switching circuit for switching between the regular voltage and the high voltage in the device.
In the operation of the EEPROM, the voltage switching circuit operates to supply the regular voltage but not high voltage to the memory cell and peripheral circuits in reading information, and to supply high voltage in erasing and writing.
Referring to FIG. 1, there is shown a circuit diagram of a conventional power supply circuit for semiconductor memory for erase/write operations. The conventional power supply circuit for semiconductor memory comprises a transfer circuit 1 for supplying an externally supplied high voltage to an internal power supply terminal V.sub.in, a transfer circuit 2 for supplying externally supplied normal voltage to the internal power supply terminal V.sub.in, booster circuit 3 for supplying predetermined boost voltage CP, an oscillator circuit 4 for supplying a pulse signal CK necessary for boosting, a level-shift circuit 5 for supplying voltage V.sub.in to the booster circuit 3, and a comparator circuit 6 for comparing difference between the potential at a power supply terminal VC and that at a power supply terminal VP.
The transfer circuit 1 is a transfer gate circuit which is formed by oppositely arranging two N-type enhancement transistors N11 and N12. When voltage vP applied to the power supply terminal VP is higher than the threshold voltage vTN of the transistor N11, the transistor N11 supplies potential vP-vTN to the internal power supply terminal V.sub.in. In addition, when high voltage vP+vTN or higher is applied to the gate of the transistor N12, the voltage vP is supplied to the internal power supply terminal V.sub.in as is.
The transfer circuit 2 is formed by an N-type depletion transistor N21. When it is assumed that the transistor N21 has a gate voltage of vG, a drain voltage of vD, a source voltage of vS, and a threshold voltage of vTD, it becomes nonconductive only when conditions .vertline.vG-vD.vertline.&gt;vTD and .vertline.vG-vS.vertline.&gt;vTD are satisfied; otherwise, it becomes conductive.
The booster circuit 3 comprises N-type transistors N31 and N32 which are serially connected, each of which is diode-connected, and the channel of which is not doped with impurities (nondoped), an N-type enhancement transistor N33, a P-type enhancement transistor P31, a zener diode D31, and a capacitance C31 connected at the serial connection point A1 of the transistors N31 and N32.
The transistor P31 is controlled by a signal S1 supplied from the level-shift circuit 5. The transistor supplies the voltage at the terminal V.sub.in to the transistor N31 when the signal S1 is at the L level, and does not supply it when the signal S1 is at the H level. Because the transistors N31 and N32 are nondoped, their threshold voltage is substantially -0.3 V. The gate of each of the transistors N31 and N32 is connected to an electrode of the terminal V.sub.in, that is, the drain. When the potential level of each drain is higher than that of the source, the transistors N31 and N32 are conductive, and otherwise nonconductive. Moreover, the capacitance C31 increases or decreases the potential at the series connection point A1 in response to the supply of the pulse signal CK. Thus, the maximum value of the boost voltage CP, which is an output signal, is voltage vI of an internal power supply VI added to the amplitude of the pulse signal CK. This voltage CP is limited by the zener diode D31 to not exceed a breakdown voltage. In addition, the transistor N33 discharges the boost voltage CP in response to H level of a signal BV supplied from the comparator circuit 6.
The oscillator circuit 4 consists of a NOR gate G41, inverters I41 and I42, a resistor R41, and a capacitance C41. The oscillator circuit 4 stops oscillation when the input signal BV is at the H level so that the pulse signal CK stops and makes its potential level the L level, while it starts oscillation when the signal BV is at the L level so that the pulse signal CK is supplied.
The level-shift circuit 5 consists of P-type enhancement transistors P51 and P52, N-type enhancement transistors N51 and N52, and an inverter I51.
The level-shift circuit 5 functions to shift the level of the signal BV from the level of the voltage vC applied to the power supply terminal VC to the voltage level at the terminal V.sub.in. Therefore, the level-shift signal S1 is at the L level when the signal BV is at L level, while it is at the voltage level at the terminal V.sub.in when the signal BV is at H level.
The comparator circuit 6 consists of an N-type non-doped transistor N61 having the drain and gate connected to the power supply terminal VP, a P-type enhancement transistor P61 having the gate connected to the power supply terminal VC and the source connected to the source of the transistor N61, an N-type enhancement transistor N62 having the gate connected to the power supply terminal VC and the drain connected to the drain of the transistor P61, and an invertor I61. When the voltage vP becomes sufficiently higher than the voltage vC, the transistor P61 is conductive, and the input of the inverter I61 is at the H level. Therefore, the comparison signal BV is at the L level. On the contrary, when the voltage vP becomes below a setting level, the transistor P61 is shut off, and the input of the inverter I61 is at the L level so that the comparison signal BV is at the H level.
The operation of the conventional power supply circuit for semiconductor memory will be explained in the following sections with reference to FIG. 2 and Table 1. The power supply voltage supplied to the internal power supply terminal V.sub.in varies depending on the potential levels at the power supply terminal VC and VP. The voltage vC at the terminal VC takes two values of Vl (about 0-2 V) and Vh (about 5 V), while the voltage vP at the terminal VP takes three values of V1 (about 0-2 V), Vh (about 5 V) and Vhh (about 12 V). The combination of the voltage vC and vP can provide six states A, B, C, D, E, and F as shown in Table 1.
Of the states A to F, states which the user usually uses for applying voltage are the states A, C, and F. That is, state A is used for the normal read operation, state C for erase/write operations, and state F for the noncooperation.
State B is not usually used, but provides the same result as state A. States D and E cause problems in the conventional power supply circuit.
TABLE 1 ______________________________________ Transfer circuit State vC vP 1 2 V.sub.in ______________________________________ A Vh V1 X O vC B Vh Vh X O vC C Vh Vhh O X vP D V1 Vhh O O Indefinite E V1 Vh O O Indefinite F V1 V1 O O vC ______________________________________ V1 = 0-2 V, Vh = 5 V, Vhh = 12 V O: Conductive, X: Nonconductive
Each operation in states A-F will be explained in detail. First, in state A, because the voltage vP is low relative to the voltage vC, the comparison signal BV output by the comparator circuit 6 becomes the H level. This makes the transistor N21 in the transfer circuit 2 conductive to supply the voltage vC (Vh) to the terminal V.sub.in. At this point, the oscillator circuit 4 stops oscillation in response to the H level of the signal BV, and makes the signal CK the L level (GND). In addition, because the signal BV is at the H level, and the voltage at the terminal V.sub.in is vC (Vh), the level-shift circuit 5 outputs the output signal S1 at the H level (Vh). Thus, in the booster circuit 3, the output signal CP remains at the L level (GND) because the signal S1 is at the H level (Vh), and the signal CK is at the L level. Therefore, the transfer circuit 1 is shut off, and the transfer circuit 2 is conductive to supply the voltage vC to the terminal V.sub.in.
In state B, because the voltage vP equals the voltage vC, the signal BV is at the H level. Therefore, this state performs the same operation as state A, that is, operation to supply the voltage vC to the terminal V.sub.in.
State C is a state where the voltage vP=Vhh, and the voltage vC=Vh, and, therefore, the comparison signal BV, becomes the L level. This causes the transistor N11 of the transfer circuit 1 to supply potential vP-vTN to the terminal V.sub.in. At this point, the oscillator circuit 4 starts oscillation in response to the L level of the signal BV and supplies the pulse signal CK. In addition, the level-shift circuit 5 outputs the output signal S1 at the L level in response to the signal BV at the L level. Thus, the booster circuit 3 is supplied with the voltage vP, and provides the boost voltage CP as its output in response to the supply of the pulse signal CK. When the potential of the boost voltage CP exceeds vP+vTN, the transistor N12 becomes conductive so that the voltage vP (Vhh) is supplied to the terminal V.sub.in as is.
Each of states D, E, and F is a state where the voltage vC at the terminal V.sub.in is V1, and where all of the circuits using the voltage vC, that is, the oscillator circuit 4, the level-shift circuit 5, and the comparator circuit 6, do not operate. Thus, the pulse signal CK of the oscillator circuit 4 and the output signal BV of the comparator circuit 6 become the L level. In addition, the output signal S1 of the level-shift circuit 5 varies depending on the voltage vI, and its signal level is vP-vTP where vTP is the threshold of the transistors P51 and P52.
In states D and E, the transistor N11 of the transfer circuit 1 becomes conductive to supply the potential vP-vTN to the terminal V.sub.in. However, because the terminal V.sub.c is at voltage level V1 and does not satisfy the nonconduction condition, the N-type depletion transistor N21 of the transfer circuit 2 is conductive. Then, the current to be primarily shut off or the leakage current flows from the terminal V.sub.in to the terminal VC. As a result, the voltage at the terminal V.sub.in has an indefinite value which is determined by the split ratio of conduction resistance of the transistors N11 and N21 as indicated by the broken line in FIG. 2.
In state F, the transfer circuit 1 becomes non-conductive, the transfer circuit 2 becomes conductive, and the voltage at the terminal V.sub.in becomes vC (V1).
The conventional power supply circuit for semiconductor memory described above has a switching circuit for selectively supplying either one of the supply voltage for regular operation and the boost supply voltage for erase/write operations to an internal power supply. In states D and E, however, there arises a disadvantage such that an uncontrollable current or leakage current is generated from the internal power supply terminal to the power supply terminal for regular operation so that the internal power supply becomes indefinite.